FIG. 1a (Prior Art) shows a depiction of a bus 120. A bus 120 is a “shared medium”, multi-drop communication structure that is used to transport communications between electronic components 101a-10Na and 110a. Shared medium means that the components 101a-10Na and 110a that communicate with one another physically share and are connected to the same parallel signals electronic wiring composing bus 120. That is, wiring 120 is a shared resource that is used by any of components 101a-10Na and 110a to communicate with any other of components 101a-10Na and 110a. For example, if component 101a wished to communicate to component 10Na, component 101a would send information along wiring 120 to component 10Na; if component 103a wished to communicate to component 110a, component 103a would send information along the same wiring 120 to component 110a, etc.
Computing systems have traditionally made use of multi-drop busses. For example, with respect to certain IBM compatible PCs, bus 120 corresponds to a PCI bus where components 101a-10Na correspond to “I/O” components (e.g., LAN networking adapter cards, MODEMs, hard disk storage devices, etc.) and component 110a corresponds to an I/O Control Hub (ICH). As another example, with respect to certain multiprocessor computing systems, bus 120 corresponds to a “front side” bus where components 101a-10Na correspond to microprocessors and component 110a corresponds to a memory controller and bridge to IO buses.
For multi-drop buses, information is transferred synchronously (with respect to a single clock edge, multiple clock edges, or even using source agent transmitted strobe edges) over parallel signal conductors such that external bus-monitoring tools (logic analyzers) electrically attached to the bus are able to record precisely what the device transmits and senses on the bus at each relevant clock edge. As result, there is no ambiguity between externally captured trace content vs the synchronous input/output values internal to the bus agents.
Owing to artifacts referred to as “capacitive loading” and “non-uniform transmission line signal integrity degradation”, busses are less and less practical as computing system speeds grow. Basically, as the capacitive loading of any wiring increases, the maximum speed at which that wiring can transport information decreases. That is, there is an inverse relationship between a wiring's capacitive loading and that same wiring's speed. Each component that is added to a wire causes that wire's capacitive loading to grow. Likewise, at increased frequencies, transmission lines forming the bus experience increased signal integrity degradation as result of topology complexities (discontinuities at branches and any other points where the impedance of the transmission line changes), high frequency losses in dielectrics, inter-signal coupling, and other high frequency effects. Thus, because multi-drop busses typically couple multiple components, bus wiring 120 is typically regarded as being heavily loaded with capacitance as well as having other transfer rate limiting signal degradation problems.
In the past, when computing system clock speeds were relatively slow (for example, below 100 MHz), the capacitive loading and other degrading effects on the computing system's busses were not serious issues because the degraded maximum speed of the bus wiring (owing to capacitive loading and other degrading effects) were still a fair match for transfer rates necessary to accommodate the computing system's internal clock speeds. The same cannot be said for many of today's computing systems. That is, with the continual increase in computing system clock speeds over the years, the speed of today's computing systems are reaching (and/or perhaps exceeding) the maximum speed capabilities of wires that are heavily loaded with capacitance and/or exhibit other high frequency degradation effects (such as bus wiring 120).
Therefore computing systems are migrating to “link-based” component-to-component interconnection schemes. FIG. 1b (Prior Art) shows a comparative example of a point to point links interconnected system vis-à-vis the multi-drop configuration in FIG. 1a. (Prior Art) According to the approach of FIG. 1b, (Prior Art) computing system components 101a-10Na and 110a are interconnected through a network 140 of high speed point-to-point links 1301 through 130N. Each point-to-point link comprises a first unidirectional point-to-point link that transmits information in a first direction and a second unidirectional point-to-point link that transmits information is a second direction that is opposite that of the first direction. Because a unidirectional point-to-point link typically has a single endpoint at each end, and a simple unbranched topology, its capacitive loading and other high frequency degradation effects are substantially less than that of a shared media bus.
Each unidirectional point-to-point link can be constructed with copper or fiber optic cabling and appropriate drivers and receivers (e.g., single or differential line drivers and receivers for copper based cables; and LASER or LED Electrical/Optical transmitters and Optical/Electrical receivers for fiber optic cables, etc.). The network 140 observed in FIG. 1b (Prior Art) is simplistic in that each component is connected by a point-to-point link to every other component.
In more complicated schemes, the network 140 has additional elements such as link repeaters and/or routing/switching nodes. Here, every component need not be coupled by a point-to-point link to every other component. Instead, hops across a plurality of links may take place through repeaters and/or routing/switching nodes in order to transport information from a source component to a destination component. Depending on implementation, repeaters and routing/switching functions may be stand alone functions within the network or may be integrated into substantive components of the computing system (e.g., processor, memory controller, I/O unit, etc.).